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These 're exclusive for bus or you can increase them for your commercial computer. Whether you know caused the satisfaction or as, if you are your German and complex members maybe diagnostics will be exclusive fundamentals that take completely for them. DLLs are unconditionally stable time-delay circuits and capable of generating delayed output signals that have a precise phase relationship with an input reference signal by employing phase interpolation Xanthopoulos ; Yang The main advantage of using the DLL is that the generated time delay is exceptionally stable against PVT variations and noise sources compared to other types of delay elements Markovic et al.

In general, analog DLLs are capable of generating a high-resolution delay step Jia with low jitter Jia ; Yongsam et al. Moreover, they have higher power supply and substrate noise rejection Jia However, they are affected at large by process variations Kuo-Hsing and Yu-Lung An analog DLL circuit is shown in Fig. Referring to Fig. The phase of the delayed output signal is compared with that of the input clock signal by the PD.

Consequently, the time delay of each delay element is varied. Repeating this mechanism through the negative feedback closed-loop, the phase error is gradually minimized until it becomes zero. Analog delay-locked loop architecture Jovanovic et al. DLLs are characterized by four performance metrics, namely, lock range, locking time, jitter performance, and static phase error Cheng and Milor The locking time refers to the time required for a DLL to reach a stable locking state from an initial state.

Thus, jitter and delay resolution is closely related Jia ; Otsuji and Narumi Finally, static phase error indicates the phase delay difference between the output delayed signal of the VCDL and the input signal to the DLL. Nonetheless, some static phase error is introduced because of the limited resolution of the PD and the CP. Static phase error is very sensitive to device speed and temperature as slow devices and high temperature result in slow switching of the transistors, thus contributing to large static phase error Cheng and Milor The delay step is controlled by the CP voltage.

Consequently, and according to the current ratio relationship in Eq. Basically, in order to achieve a long delay range, the VCDL should produce long delays. There are essentially two techniques to design the VCDL for this objective. The first technique is by utilizing a large number of delay elements having a comparatively short unit delay. The drawbacks of this method are increased power consumption and area. The second method utilizes a smaller number of delay elements with a considerably long unit delay.

However, this has the shortcoming of producing signals with slow-switching transition edges which are more prone to deteriorate jitter performance of the unit delay element Jaehyouk et al. Diode-connected transistors have also been used as delay elements.

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MOS diode-based delay element Markovic et al. The output of an inverter is loaded with a diode-connected pMOS transistor. Another type of delay elements in which the delay is varied by regulating the supply voltage is shown in Fig. Accordingly, for variable supply voltages, the transistors of the logic gates are allowed to draw variable current values, therefore changing the rate at which the output effective capacitance is charged or discharged.

This leads to a tunable delay for the delay element. However, one of the limitations of this technique is that it needs an adjustable analog voltage source capable of providing a considerable amount of current Nuyts et al. Another limitation is the highest achievable delay resolution which is not as fine as that of the other delay-controlling techniques reported in this paper Moazedi et al.

Tunable logic gate-based delay element based on supply modulation Yang It has a good robustness against environmental variations because this architecture is current-controlled rather than voltage-controlled Junmou et al.


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It also produces long-range delays where the delay range is directly proportional to the lengths and the number of transistors in the N pull-down network Kim et al. It is summarized that the delay elements are the fundamental building blocks for the CMOS delay lines. For delay-tuning functions, there are two main strategies which are changing the drive strength of the delay element and load-increasing strategy.

Analog-tunable delay elements are the recommended choice when high-resolution delay step, low jitter, good intrinsic calibration for PVT variations and good stability are considered together in the design. Apart from analog-controlled delay elements, digitally-controlled delay elements are also being developed as they offer robustness and simplicity when it comes to design and delay control.

The next section discusses these circuits in detail. These types of delay elements are designed using logic gates. Delay is controlled using a digital word, where ideally a linear binary increment of the word corresponds to a linear increment of output delay. There are four main types of picosecond-resolution delay elements which are the shunt-capacitor inverter SCI , current-starved inverter CSI , inverter matrix, and the differential delay cell DDC Abas et al. By selecting the capacitors through control pins A 1 through A N , the load can be varied, therefore changing the rise and fall times of the inverted input signal.

This signal then passes through the output inverter which inverts the signal back to resemble the input but with added fine delay Abas et al. In another implementation of this type of delay elements in 0. An SCI-based delay element Abas et al. The CSI architecture is shown in Fig.

The current mirrors are used to separate the set of current source from the inverters-based buffer stage. The current through load transistor M6 which is connected to the current mirrors can be changed via parallel connected transistors, M1—M5. These transistors also act as binary-weighted resistors and signals A, B, C, D, and E allow control of their total resistance, hence modifying the currents through M10 and M11, resulting in a change in the speed and response of the inverters. Although the idea of using binary weighted transistors to precisely control delay step sounds attractive, linear step increments are only possible by fine-tuning the size of transistors M1 through M5 as interaction of parasitic capacitance of these transistors affects the binary weights, causing non-linear delay steps.

Another implementation that produces small delay steps is the inverter matrix, as shown in Fig. It is composed of an even number of parallel tri-state inverter banks. The delay of the circuit is adjusted by switching in and out the required number of inverters from the bank Abas et al. This configuration implemented in 0. The DDC, sometimes referred to as the variable-resistor array-based delay cell, is shown in Fig. A differential variable-resistor array delay element Saint-Laurent and Swaminathan Similar to the SCI implementation, the delay-controlling transistors are used to control the output rise and fall times via digital inputs applied to the gates of these transistors that form the variable-resistor array.

For example, by turning OFF the transistors, the effective resistance of the variable-resistor array is increased, resulting in increased time delay. This change in the parasitic capacitance can lead to non-monotonic delay behavior with ascending binary pattern of the digital input vector Maymandi-Nejad and Sachdev Likewise, as mentioned in the previous section, phase interpolation can also be implemented by utilizing digital DLLs as delay lines.

A sub-gate delay resolution can be achieved by the digital DLLs Eto et al. A digital DLL has the advantages of having simpler and more robust design, shorter design time, requiring lower supply voltages therefore, having a significant reduction in power consumption , having wider range of delay regulation, and enabling better process portability Jia ; Jovanovic et al.

A digital DLL circuit is shown in Fig. Digital delay-locked loop architecture Jovanovic et al. The main difference between analog and digital DLLs is the locking system, or sometimes called the control module as it is responsible for controlling the delay of the delay line based on the output of the PD.

Moreover, analog DLLs generally have smaller footprints as well as better delay resolution, linearity, and jitter performance than digital DLLs. It is summarized that, like analog-tunable delay elements, digitally-controlled delay elements can also produce high-resolution delay steps according to the current ratio relationship of Eq.

This is because of the change in the complex parasitic capacitance of the digitally-controlled transistors responsible for delay tuning when these transistors are turned ON and OFF. This challenge is mainly noticed with the variable-resistor array delay element Zhang and Kaneko ; Maymandi-Nejad and Sachdev Nonetheless, this drawback may not be applied provided that proper design techniques are utilized, as in the case with the digitally-controlled SCI delay element implemented by Miao et al.

The digitally-controlled delay elements have the upper hand when good process portability, short design time, simple and robust design, and good power management are considered together in the design. This is clearly recognized in TDLs as the delay resolution of these types of CMOS delay lines relies on the propagation delay of the logic-gates based delay elements.

On the other hand, degradation of the jitter performance can be the main penalty of the CMOS technology scaling. This is attributed to the noticeably increasing effects of interconnect resistance, NBTI, random doping fluctuations, time-dependent dielectric breakdown TDDB , hot-carrier injection HCI degradation, gate-oxide tunneling, PVT variations, physical-level changes, and short channel effects Jiang ; Segura et al.

The following sub-sections address two main areas affecting delay resolution with regards to CMOS technology scaling. As a simple observation, according to Eq. On the other hand, Eq. In Eq. Therefore, it is recommended to investigate the main parameters which are directly influencing I D. This is clearly explained later in this sub-section. Although it seems that only the change in threshold voltage effects delay as different CMOS technology is used, there are other factors that relate technology scaling to delay resolution and they all are linked with the change in threshold voltage.

These factors include the change in oxide thickness and dopant density as we migrate between different CMOS technologies. For example, a decrease in T ox causes an increase in gate oxide capacitance, C ox. This is clearly explained by the following equation Segura and Hawkins ; Rabaey et al. Furthermore, the increase in C ox implies an increase in the drain saturation current I Dsat as illustrated in the following relationship Segura and Hawkins ; Rabaey et al.

According to Eq. According to Eqs. This again affects the threshold voltage in line with what has been discussed for Eq. It can be concluded that as CMOS technology scales down, the gate delay also decreases as a result of the decrease in threshold voltage due mainly to the change in oxide thickness and carrier mobility. As CMOS technology features smaller transistors and lower power supply voltage, interconnecting metal wires also become thinner. In relations to delay line design, this causes the undesired increase in interconnect resistance which ultimately affects the total gate delay.

The interconnect width and thickness are inversely proportional with the interconnect resistance. Thus, for a fixed interconnect length, the interconnect resistance increases as w and t decreases. This network model is shown in Fig. In DSM processes, this resistance reaches several hundreds of ohms.

Accordingly, it is concluded that interconnect length and width play a main role in determining the gate delay of digital circuits. This opens the possibility of designing interconnect arrays of various sizes to allow high-resolution delay step for CMOS delay lines, as shown in Fig. For example, if S 1 is activated, R w is reduced to a half of its value compared to when S 0 is activated.

The layout of these binary-weighted wires should be considered during the design process to avoid the effects of coupling. Activating two adjacent switches results in forming two adjacent parallel wires, which may in turn lead to unwanted signal coupling effects that will degrade the delay resolution.

Signal coupling results in fluctuation of R w which ultimately changes the time constant value. Another quantity that must be considered in the design is thermal noise whose RMS voltage equation is given by:. At high operating frequencies and according to Eq. In deep sub-micrometer digital circuits, the delay of both logic gates and interconnects is increasingly affected by parameter process and environmental variations and noise sources.

On the other hand, environmental variations occur during the operation of a circuit and are caused by power supply voltage fluctuations and temperature variations that modify the characteristics of transistors in a circuit Orshansky et al. The aforementioned process, supply voltage, and temperature variations are often referred to as PVT variations. The proceeding sub-sections discuss the effects of these variations on CMOS delay line performance. Process variations are subdivided into inter-die and intra-die variations Segura et al. Process gradients over the wafer Eisele et al.

The variations in transistor speed cause the delays for nMOS and pMOS transistors to be different, causing transient fluctuations at the output known as jitter. The jitter level should be taken into consideration as it directly affects delay resolution Nuyts et al. On the other hand, intra-die variations, also called local variations, cause different devices within the same chip to have different properties. Statistical variations of doping concentrations, line edge roughness Henzler a and proximity effects are examples of intra-die variations Alioto et al.

To illustrate this, the random variations in the threshold voltage are significantly increased as the presence or absence of a single atom of the dopant atoms will have a more significant effect on the overall device performance compared with large-scale CMOS technologies Ghahroodi For transistors located closely to each other, these variations are usually correlated Nuyts et al. Random intra-die variations, such as random doping variations, impact devices such as transistors and interconnects in a different way even in the case they are relatively close. Systematic variations, such as proximity effects and metal density variations, impact close devices transistors in the same way Alioto et al.

These local process variations lead to device mismatch, which in turn leads to degraded delay resolution due to excessive jitter. The output drawn in solid line is the ideally delayed output of 4 T u. However, the output drawn in dotted lines is delayed by 4 T u plus the delay uncertainty introduced by subsequent delay stages. In other words, Fig. In Fig. For a multiple-stage delay line, the delay deviations and uncertainties are strongly correlated, meaning that they accumulate along the delay stages.

In the case that the delays of the stages vary independently, the standard deviation is written as Nuyts et al. They are quantities for measuring systematic errors that cause the delay increments to differ from their ideal values Li ; Jansson et al. DNL can be defined as the delay deviation of the i th delay step from its ideal value T u.

DNL indicates the precision of a delay line output according to its input code. On the other hand, INL is defined as the deviation of the n th delay step position from its normalized ideal value determined by a straight line connecting the first and the last steps. It specifies the linearity of the overall delay line Li ; Nuyts et al. Many high-speed and high-performance CMOS VLSI circuits impose strict linearity requirements represented by the achievement of highly-monotonic and linear delay steps by the designed CMOS delay line for the entire attainable delay range Sakamoto et al.

Hence, DNL can directly be obtained by the delay variation of a particular delay element as Henzler a :. As shown in Eqs. On the other hand, when utilizing a DLL as a delay line, the locking system of the DLL forces the delay to be locked to a specific value regardless of any intra-die or inter-die variations. This implies that the total jitter of the delay line is forced to be zero although the delay uncertainty for the individual delay elements is not equal to zero and is given by:. Environmental variations sources can vary in time and space according to the power consumption, and they highly contribute to the delay uncertainty Segura et al.

This results in increased power supply noise and ultimately increases jitter.


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On the other hand, the fluctuation in the output time delay due to temperature variations is attributed to two processes: threshold voltage variation and carrier mobility fluctuation Segura et al. The threshold voltage magnitude is reduced as temperature increases as illustrated in the following equation Weste and Harris b :. The threshold voltage reduction is accompanied by a relative increase in drain saturation current due to the increase in gate overdrive voltage, V GS — V TH Segura et al. This also implies a reduction in the gate delay according to Eq. On the other hand, the relationship between the carrier mobility and the temperature is formulated as follows Weste and Harris b :.

It is obvious from Eq. For example, when temperature increases, the mobility is decreased, resulting in slow switching of the transistors of the delay elements. Hence, the propagation delay is increased and vice versa Kumar and Kursun ; Segura et al. For the aforementioned description about the PVT variations, it can be summarized that these variations highly affect the jitter performance and delay resolution of the CMOS delay line.

Therefore, it should be noted that the total delay fluctuations due to these variations are required to be less than the delay resolution in many applications especially for the high-resolution and high-frequency applications Zhang and Kaneko In CMOS delay lines, the deviation of the output pulse amplitude is known as amplitude noise and the deviation of the output time delay is known as timing jitter. The noise sources are classified into two: physical noise sources and circuit design-induced noise sources. Physical noise, also called intrinsic noise, is caused by the random fluctuation and stochastic nature of electronic charge carriers implanted in the device during fabrication.

It may be reduced but cannot be eliminated completely Li ; Figueiredo and Aguiar ; Henzler a. It is the main source of jitter in delay lines. Physical noise causes delay shifts in the output signal of the CMOS delay line. The effect of these delay shifts on the delay step is explained by assuming that each delay element contributes to a certain noise error-induced delay shift which accumulates along the delay line Henzler a :.

On the other hand, circuit design-induced noise, also called non-intrinsic noise, is due to circuit switching activities that cause fluctuations in currents and voltages. This noise can be minimized and even removed if careful design techniques are utilized.

This noise can be classified into many subclasses, namely, power supply and ground lines noise, leakage noise, charge-sharing and coupling noise, duty-cycle distortion DCD , electromagnetic interference EMI , and reflections Shepard and Narayanan ; Figueiredo and Aguiar ; Li All of these noise sources ultimately contribute to timing jitter. Timing jitter is classified into three types: absolute jitter, cycle jitter, and cycle-to-cycle jitter Zhang et al. It is written as:.

Jitter due to noise can be classified into random jitter and deterministic jitter. Random jitter, also referred to as non-systematic jitter, is an unpredictable jitter component whose amplitude is unbounded and Gaussian in nature. On the other hand, deterministic jitter, also known as systematic jitter, is a predictable jitter component whose amplitude is bounded. Physical noise sources are considered as the major contributor to random jitter in CMOS delay lines. Circuit design-induced noise sources also contribute to random jitter; however, they contribute more to deterministic jitter through DCD, EMI, charge-sharing and coupling noise.

Device mismatch caused by intra-die process variations also contributes to deterministic jitter Jia ; Li The influence of noise on jitter is strongly related to the output load capacitance and the short-circuit current of the delay line. The total jitter of a delay line can be obtained by the sum of variances of the time delay produced by each delay stage if the noise sources are uncorrelated.

However, these jitter components are correlated through the power supply rails and their respective noise components. Taking this into consideration, the total jitter is higher because of the correlation effect Figueiredo and Aguiar It has been shown that there is a trade-off between delay resolution and dynamic range for the different types of delay line circuits.

In other words, a higher-resolution delay line will have a shorter dynamic range and vice versa. Consequently, this reflects the necessity of developing a CMOS delay line circuit which fulfills each of these delay specifications in one single circuit block. Some suggestions regarding this trade-off challenge are discussed at the end of this section. Moreover, analog-tunable delay elements have lower jitter and better intrinsic calibration for PVT variations Markovic et al. Fine delay control according to current ratio relationship of Eq.

However, this might be achieved but at the cost of linearity degradation as the complex parasitic capacitance of the digitally-controlled transistors changes when the transistors are turned ON and OFF Maymandi-Nejad and Sachdev Furthermore, the jitter performance of the digitally-controlled delay elements is not as fine as that of the analog-tunable delay elements. This is because that for a high-resolution digital delay line, if the controller always switches the control code of the delay line, the jitter performance will not be good. Alternatively, digitally-controlled delay elements have wider range as well as simpler control of delay regulation, simpler and more robust design, lower power consumption, and better process portability than analog-tunable delay elements.

Programmable delay lines with sub-gate delay resolution have been realized using many circuit topologies and techniques. They mainly involve: changing the capacitive loading SCI mechanism reported in Schidl et al. As illustrated in this study, the jitter performance is dependent on the PVT variations and noise sources of the delay line circuit. However, another important factor that affects the jitter performance is how the CMOS delay line is controlled, i. These delay elements are all digitally-controlled and implemented using 0. To illustrate this, sequence number 1 refers to the best case, number 3 to the worst case, and number 2 to in between case.

The following descriptions compare and discuss the differences in the performance among these delay elements with respect to the design specifications starting with delay resolution and ending with robustness against temperature variation. To start with, the resolution of the inverter chain is dependent on the CMOS process, thereby limiting the maximum achievable resolution of inverter-based buffer to approximately tens of picoseconds.

Design of PVT tolerant inverter based circuits for low supply voltages - Semantic Scholar

For a specific required delay range, a large number of redundant inverters is required by the Inverter Chain and hence, higher power is consumed and larger area is occupied. The power consumption and the area are increased for the SCI when the delay increases since a heavy load capacitance is needed. However, a lower power is consumed when a larger delay is required for the CSI Zhang and Kaneko The effect of process variations on the delay steps between delay stages of the Inverter Chain is considered small compared to the relatively large delay step of the inverter-based buffer.

Thus, the Inverter Chain achieves better linearity compared to the SCI and CSI in which the minimum attainable delay step is much smaller than that of the inverter chain Zhang and Kaneko When both discharging and charging paths of the CSI contain digitally-controlled transistors, the effect of complex parasitic capacitance interaction becomes more noticeable and leads to more delay fluctuations than the SCI especially when the delay increases. The inverter chain has a poor robustness against temperature changes as the resulted delay fluctuations accumulate along the delay line in a correlation relation.

However, a heavy load can be utilized for the SCI to enhance the robustness against the temperature variations but at the cost of increased power consumption and area Zhang and Kaneko Back to the trade-off challenge between delay resolution and delay range, some solutions are being proposed in order to overcome this challenge.

Cascading multiple delay lines with different specifications is one of the possible solutions Xanthopoulos et al. For example, a coarse counter is cascaded with interpolators based on digital delay lines Kalisz Another solution is to employ both analog and DCDLs together in one single design to make use of the unique advantages of both of these differently controlled CMOS delay line types Markovic et al. A combination of integrated CMOS delay lines technique with other time-interval generation techniques as in Klepacki et al.

It should be mentioned that the benefits gained from utilizing these possible solutions are achieved at the cost of potential increasing in power consumption, occupied area, jitter, non-uniform linearity, and control complexity. Depending on the requirements of the applications in which these delay lines are employed, these shortcomings may be acceptable and compromised in favor of achieving both high delay resolution and wide delay range. All authors contributed equally to this work. All authors read and approved the final manuscript. Bilal I. Abdulrazzaq, Email: moc. Izhal Abdul Halin, Email: ym.

Shoji Kawahito, Email: pj. Roslina M. Sidek, Email: ym. Suhaidi Shafie, Email: ym. Nurul Amziah Md.